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Unintentional clock skew caused by variability can result in degraded and unreliable system performance. In this paper, we present a deskewing technique that continuously senses and compensates for unintentional clock skew. It uses an enhanced skew detector block that detects the skew magnitude in addition to the phase. This helps eliminate the need for complex feedback control, thus reducing the...
An in-situ self-aware adaptive power control (APC) system is presented in this paper. This APC system consists of a voltage sensor, a variable threshold comparator, slack detection circuits and control signal generators to control a set of bi-directional shift registers. The values stored in bi-directional shift registers are used to control the status of multi-mode power gating network. This APC...
In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the most effective methods for power (and area) reduction in CMOS digital circuits. Recently, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft-error rates caused by single-event...
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