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Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert...
Worst-case design uses extreme process corner conditions which rarely occur. This limits maximum speed specifications and costs additional power due to area over-dimensioning during synthesis. We present a new design synthesis strategy for digital CMOS circuits that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning...
An ultra-low voltage performance of nanowire-transistors-based CMOS circuits is investigated using the Spice model parameters. All Spice model parameters of BSIM4 are extracted from measurement data of nanowire transistors fabricated on 300 mm SOI wafer. The delay time and the power consumption of NW-Tr.-based and bulk-Tr.-based CMOS circuits are examined. The operation voltage of NW-Tr.-based inverter...
Test technologies for integrated circuits have traditionally tried to maximise test data compression rates, because these are essential for keeping test time and costs low. However, power consumption during the test process is a problem that has been addressed on recently. Excessive power consumption may result in thermal stress and increased voltage drops within the circuit, which implies increasing...
Worst-case design uses extreme process corner conditions which rarely occur. This costs additional power due to area over-dimensioning during synthesis. We present a new design strategy for digital CMOS IP that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. Dynamic...
The use of multiple voltage domains in an integrated circuit has been widely utilized with the aim of finding a tradeoff between power saving and performance. Level shifters allow for effective interfacing between voltage domains supplied by different voltage levels. In this paper we present a low power level shifters in the 90 nm technology node capable of converting subthreshold voltage signals...
This paper presents a high performance 16times16 bit 2's complement multiplier using MOS current mode logic (MCML). A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, MUX and full adder are designed and optimized for low power and high-speed operation. Using these gates, a 16 bit MCML signed multiplier is designed and tested for 4 different supply current, in a UMC 0.18 mum CMOS...
In this paper a new full adder (FA) circuit optimized for ultra low power operation is proposed. The circuit is based on modified XOR gates operated in the subthreshold region to minimize the power consumption. Simulated results using 65 nm standarad CMOS models are provided. The simulation results show a 5%-20% for frequency ranges from 1 KHz to 20 MHz and supply voltages lower than 0.3 V.
An in-situ self-aware adaptive power control (APC) system is presented in this paper. This APC system consists of a voltage sensor, a variable threshold comparator, slack detection circuits and control signal generators to control a set of bi-directional shift registers. The values stored in bi-directional shift registers are used to control the status of multi-mode power gating network. This APC...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
This paper presents the design of a wide band two-stage CMOS voltage-controlled ring oscillator based on the Maneatis cell. The VCO is designed for a frequency synthesizer module that generates local oscillation (LO) frequencies over a large bandwidth, targeting a multi-band acquisition system. The goal is a wide operating frequency tuning range of 400 MHz - 1.4 GHz in the VCO with low power consumption,...
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