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We abstract the I/O functionality of continuous-time dynamical systems (e.g., SPICE netlists with combinational and sequential logic) as Finite State Machines (FSMs). This enables efficient simulation of large designs implemented with less-than-perfect devices and components, and also opens the door to formal verification of transistor-level designs against higher-level specifications. In particular,...
As technology is scaled down, supply voltage and gate capacitances are reduced which degrades the reliability of the circuits. For near sub-threshold region design, this causes even more serious reliability issues because the supply voltage is reduced to near the threshold voltage of the devices. Soft error is one such phenomenon which changes internal node voltage due to external noise. Hence it...
Synchronizer characterization is non-trivial. The exponential response to parameter changes makes this task a challenge, which is further hampered by numerical instability and precision limitations of circuit simulators. The analysis of multi-stage synchronizers is extremely difficult due to the compounding of these exponential factors. We present results and discoveries from analyzing a variety of...
In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We...
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