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Three-dimensional (3-D) integration is a promising technology to alleviate the interconnect bottleneck by stacking multiple dies in a monolithic fashion. Both power dissipation and delay can be reduced by utilizing the third dimension where through silicon vias (TSVs) are used for vertical communication. Characteristics of switching noise that couples to a sensitive device due to a TSV are investigated...
Current propagation within a lightly doped substrate is approximated with a half-ellipse to efficiently estimate substrate resistances. As opposed to existing work, the proposed model contains only one fitting parameter. Compact models are also developed to determine the isolation efficiency of several commonly used structures such as a guard ring and triple well. The accuracy of these models is verified...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
Design and characterization of a new generation of single-photon avalanche diodes (SPAD) array, manufactured by ST-Microelectronics in Catania, Italy, are presented. Device performances, investigated in several experimental conditions and here reported, demonstrate their suitability in many applications. SPADs are thin p-n junctions operating above the breakdown condition in Geiger mode at low voltage...
Substrate noise is an important problem in single chip solution. An experimental study and a physical model describing substrate noise suppression by patterned ground shield (PGS) of inductors are presented in this paper. Different grounding methods of PGS are used to compare the different effects on substrate noise suppression. To make the design immune to substrate noise, the parasitic inductance...
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