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As location sensing devices are becoming ubiquitous, overwhelming amounts of data are being produced by the Internet-of-Things-That-Move. Though analyzing this data presents significant business opportunities, new techniques are needed to attain adequate levels of processing performance. One example is the recently introduced geohash geographical coordinate system that is mainly used for indexing...
Problems involving network design can be found in many real world applications such as power systems, vehicle routing, telecommunication networks, phylogenetic trees, among others. These problems involve thousands or millions of input variables and often need information and solution in real time. In general, they are computationally complex (NP-Hard). In this context, metaheuristics like evolutionary...
This paper presents an optimizing methodology for implementing a multi-layer perceptron (MLP) neural network in a Field Programmable Gate Array (FPGA) device. In order to obtain an efficient implementation, a compromise of time and area is needed. Starting from simulation in the learning phase with fixed point operators, we have developed a methodology which allows the automatic generation of a VHDL...
Benefit from wave union, the bins (especially the ultra-wide bins) are sub-divided by each other, making FPGA TDC achieve a resolution beyond its cell delay. At such high level resolution, delay chain becomes very sensitive to the environment disturbance, including power supply voltage, temperature and current surge. On chip calibration needs lots of events and hence cannot follow fast delay changes...
In this paper, we present several enhancements to power watermarking that allow to simultaneously transmit and verify multiple signatures. Power watermarking of netlist IP cores for FPGA architectures is used for detecting IP fraud where the signature (watermark) is transmitted over the power supply pins of the FPGA. Many (watermarked) IP cores can be combined in an FPGA design, which raises the question...
The basic principles and structure of HDB3 was briefly introduced in this paper, and the shortcomings of the existing HDB3 encoder and decoder was analyzed. Then a new design of HDB3 encoder and decoder based on FPGA was proposed, and the hardware design circuit and software simulation were introduced. The simulation was achieved through the VERILOG-HDL in EP2C35F672C8 chip of CycloneII series in...
We present a fault-tolerant post-mapping resynthesis for FPGA-based designs that exploits the dual-output feature of modern FPGA architectures to improve the reliability of a mapped circuit against faults. Emerging FPGA architectures, such as 6-LUTs in Xilinx Virtex-5 and 8-input ALMs in Altera Stratix-III, have a secondary LUT output that allows access to non-occupied SRAM bits. We show that this...
This article is based on the new standard, uses the FPGA device opening, adopts FPGA technique of EDA to build 64 bits decimal floating multiplier model. And in this article, we mainly use DPD codec and BCD new codec and Signed-Digit radix-5 to process coefficient. At last, we use Decimal 32:2 CSA algorithm to process partial product. This effectively increases the computing speed and accuracy. As...
This paper presents FPGA implementations of add/subtract algorithms for 10's complement BCD numbers. Carry-chain type circuits have been designed on 6-input LUT's Xilinx Virtex-5 FPGA technologies. Some new concepts are reviewed to compute the P and G functions for carry-chain optimization purposes. Designs are presented with the corresponding time performances and area consumption figures. Results...
While stability and robustness of synchronous circuits becomes increasingly problematic due to shrinking feature sizes, delay-insensitive asynchronous circuits are supposed to provide inherent protection against various fault types. However, results on experimental evaluation and analysis of these fault tolerance properties are scarce, mainly due to the lack of suitable prototyping platforms. Using...
This paper presents a low-power FPGA with multiple supply voltages. In the proposed FPGA, the supply voltage of each logic block is self-adaptive to the workload, data path and temperature to minimize the power consumption without system performance degradation. In the self-adaptive voltage control scheme, features of the asynchronous architecture are exploited. The data arrival of the asynchronous...
The appearance of the new MPEG-4 standard offers opportunities for real-time implementations of MPEG-4 encoders suitable for a wide range of applications, including video conferencing, digital storage media, television broadcasting, Internet streaming, and communication. With the rapid development of FPGA, SOPC has been paid great attentions in the area of image and video processing in recent years...
CRC (cyclic redundanncy check) block was developed on FPGA (field programmable gate array) in order to meet the needs for simple, low-power and low-cost wireless communication such as Zigbee. Zigbee operates primarily in the 2.4 GHz band, which makes the technology easily applicable and worldwide available. This paper gives a short overview of CRC block in the digital transmitter based on Zigbee standard...
Generally, the traditional SDRAM controllers use an arbitral form to deal with the variable accessing requirement. But the design of the arbitral form is very complex. To avoid the complexity, this article introduces a time-partition form SDRAM controller based on multi-DAB project, and compares the arbitral form controller and the time-partition form. At last, the paper analyzes the new form of SDRAM...
Implementation of concatenate code has various problems such as frame synchronization and clock utilization for design on the FPGA chip. This paper proposed an efficient design methodology for serial concatenation coding of cable systems and fabrication on the FPGA chip Vertex II pro xc2vp30-5, Xilinx.
This paper proposes an area efficient signal processing architecture to perform IDDT test calibration through vector multiplication. The design follows the field programmable array organization, and capitalizes on the unique behavior of binary encoded signals to implement compact multiply elements. Vectors with 8 bit values were multiplied at a rate of 300 kHz, independently of vector size.
RFID is now attracting many interests for its bright future in commercial. The paper introduces UHF RFID reader software design. The design used the hierarchical structure. It included the physical layer and the tag-identification layer. Physical layer is that the coding and modulation. It is described in verilog HDL language and implemented in FPGA. Tag-identification layer are commands which used...
The paper presents a formal design methodology for reconfigurable, modular digital controller logic synthesis. The project of embedded controller starts from behavioral, graphical hierarchical and concurrent state machine description in Unified Modeling Language (UML). After the hierarchical encoding of nested and concurrent superstates, the UML state machine diagram can be directly and automatically...
A design of interweave encoder based on FPGA is introduced. The Interweave Encoder Principle is described and the design simulation result is presented. It has been known that the information-bearing signal generated at the transmitter may inevitably be interpreted mistake at the receiver due to distortion of the signal in the channel between the transmitter and receiver. Therefore forward error correction...
This paper presents a system level design flow which enables rapid design space exploration and a verification tool to assist a designer to identify an FPGA-based MPSoC for stream-oriented application. The case study, JPEG encoding, illustrates how the tool exploits the task-level parallelism and produces a suitable architectural design, binding and scheduling algorithm while satisfying physical constraints.
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