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We present a fault-tolerant post-mapping resynthesis for FPGA-based designs that exploits the dual-output feature of modern FPGA architectures to improve the reliability of a mapped circuit against faults. Emerging FPGA architectures, such as 6-LUTs in Xilinx Virtex-5 and 8-input ALMs in Altera Stratix-III, have a secondary LUT output that allows access to non-occupied SRAM bits. We show that this...
While stability and robustness of synchronous circuits becomes increasingly problematic due to shrinking feature sizes, delay-insensitive asynchronous circuits are supposed to provide inherent protection against various fault types. However, results on experimental evaluation and analysis of these fault tolerance properties are scarce, mainly due to the lack of suitable prototyping platforms. Using...
The method of synthesis and implementation of Mealy FSMs into FPGAs is proposed. Synthesis is based on the architectural decomposition and multiple encoding of internal states. States are divided into subsets based on a current state and encoded separately in each subset. The state is decoded in the second-level circuit based on the multiple code and the code of a current state. It leads to implementation...
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