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This paper presents a multi-channel Digital Programmable Delay Trigger System (DPDTS) with high accuracy and wide delay range, which can be widely used in laser system and electron accelerator. This DPDTS mainly makes up of reference clock module, user interface and control module and Digital Programmable Delay Trigger (DPDT) module which is implemented on a Xilinx V6LX75T FPGA. In this DPDTS, DDS...
This paper is concerned on FPGA design for control implementations of the Single-Phase Matrix Converter (SPMC) operating as a single-phase Inverter. The Sinusoidal Pulse Width Modulation (SPWM) technique is used to synthesize the output voltage with. The power circuit uses the Insulated Gate Bipolar Transistor (IGBT) as switching device in the SPMC implementation. Safe-commutation strategy was incorporated...
Rate control mechanism is the necessary part of the Ethernet congestion management. Based on the modified token bucket algorithm, the design of a synchronous rate control circuit that is able to process the variable length frames without knowing their lengths is presented. The main part of the circuit is a large virtual token counter, which is 1024 times the token number, the key feature being that...
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