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The recent trend of reconfigurable hardware and convergence of hardware platform in embedded system have enhanced the application of FPGAs. Although the capability and performance of FPGA have advanced, the testing of FPGAs both online and off-line (manufacturer oriented testing) poses a major challenge. Importance of delay testing has grown especially for high-speed circuits. Even presence of small...
In this paper we introduce a fine-grain fault diagnosis approach for reconfigurable logic blocks. As opposed to previous works, we propose to reuse rather than to discard defective blocks. We describe methods to analyze deeper a defective Xilinx Virtex2Pro slice and diagnose the fault, out of a set of 150, that causes the malfunction. The outcome of the fault diagnosis is subsequently used to characterize...
In this paper, we present a test pattern generation method based on fault injection for logic elements of FPGAs (Field Programmable Gate Arrays). This method is able to perform fault diagnosis for stuck-at-0 and stuck-at-1 faults, which can locate logic resource faults in the logic elements of FPGA. We use EP2C8Q208C8N's LE (Logic Element) of Altera as the object to generate the test pattern, work...
Reversible logic is attracting the researchers attention for fault susceptible nanotechnologies including molecular QCA. In this paper, we propose concurrently testable FPGA design for molecular QCA using conservative reversible Fredkin gate. Fredkin gate is conservative reversible in nature, in which there would be an equal number of 1s in the outputs as there would be on the inputs, in addition...
A built-in self-test (BIST) approach is presented for the configurable logic blocks (CLBs) in Xilinx Virtex-5 field programmable gate arrays (FPGAs). A total of 17 configurations were developed to completely test the full functionality of the CLBs, including distributed RAM modes of operation. These configurations cumulatively detect 100% of stuck-at faults in every CLB. There is no area overhead...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order...
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