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This paper describes a mixed mode background calibration technique for pipeline analog-to-digital converter (ADC). The proposed calibration scheme uses an insignificant, low-speed, low-power, high-resolution sigma-delta ADC to determine error in digital domain. The calibration technique calibrates capacitor mismatch as well as finite opamp dc gain, while the digital redundancy compensates for comparator...
The pipelined architecture is one of the most popular analog-to-digital converter (ADC) architectures. Various circuit nonidealities such as finite opamp gain and mismatch in capacitors limit the pipelined ADCpsilas performance. In this paper, a new technique for the calibration of interstage gain errors in pipelined ADCpsilas are described. The proposed calibration scheme uses a slow but accurate...
A new switched-capacitor multiply-by-two amplifier with an accurate gain of two is presented. The proposed architecture requires only one opamp in four phases to generate two effective outputs. It significantly suppresses the gain error due to capacitor-mismatch and also provides a better power efficiency. Monte-Carlo simulation results are presented to confirm the feasibility of this new technique,...
Pseudo-random dithers have been used to measure capacitor mismatch and opamp gain errors of the pipelined analog-to-digital converter (ADC) in background and to calibrate them digitally. However, this error measurement suffers from signal range reduction and long signal decorrelation time. A signal-dependent dithering scheme allows the injection of a large dither without sacrificing the signal range...
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