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Recent work on ADCs targeting sampling rates of hundreds of MHz with resolutions in the range of 10 to 11 b has faced speed limitations with a single channel or employed interleaving, but with a relatively high power dissipation or low SNDR. This paper introduces a calibration technique that, together with a high-speed opamp topology, allows a single channel to operate at 500 MHz and digitize a 233...
A pipelined ADC incorporates a digital foreground calibration technique that corrects errors due to capacitor mismatch, gain error, and op amp nonlinearity. Employing a highspeed, low-power op amp topology and an accurate on-chip resistor ladder and designed in 90-nm CMOS technology, the ADC achieves a DNL of 0.4 LSB and an INL of 1LSB. The prototype digitizes a 233-MHz input with 53-dB SNDR while...
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