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Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. This paper presents a method for symmetrical FPGA placement based on ant colony optimization (ACO). Also, we take the routing congestion into consideration by introducing a congestion factor in our algorithm. Experimental results show that compared with the state-of-the-art FPGA...
In recent years, various types of ad hoc routing protocols have been studied in the mobile ad hoc networks. Specifically, the clustering hierarchical routing algorithms have been developed to increase the system performance. Hierarchical structure has inevitably brought some drawbacks, maintaining the hierarchical structure needs more complicated cluster heads selection algorithm, which may result...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
IEEE P1900.4 is an emerging standard for optimized radio resource utilization where cognitive radio technologies are used for efficient spectrum utilization. In this paper, we design and implement a cognitive wireless network system based on open documents of IEEE P1900.4, and evaluate its performance using UDP streaming and HTTP download. Our experiments show interesting results that total network...
Most network operators have considered reducing Label Switched Routers (LSR) label spaces (i.e. the number of labels that can be used) as a means of simplifying management of underlaying Virtual Private Networks (VPNs) and, hence, reducing operational expenditure (OPEX). This letter discusses the problem of reducing the label spaces in Multiprotocol Label Switched (MPLS) networks using label merging...
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