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Wireless mesh network (WMN) is a promising technology for building cost-effective and easy-deployable wireless home networking infrastructure. To efficiently utilize limited radio resources in WMNs, packet transmissions (especially, redundant packet transmissions) should be carefully managed. To this end, we introduce a software-defined WMN architecture where the data plane and control plane are separated...
Ternary Content Addressable Memory (TCAM) is a hardware device which can support high-speed table lookups and is an attractive solution for applications such as packet forwarding and classification. We investigate various TCAM architectures recently proposed for TCAM power and memory reduction in packet forwarding and show that far better power and memory performance is possible when we use an optimal...
In this paper, we study the fundamental property of the ad hoc network using connectivity index. We investigate the construction of minimum cost multicast trees by selecting a link having minimum connectivity Index and comparing application required bandwidth with (available bandwidth - allocated bandwidth) of the link. We have shown that Increase in total connectivity Index of the entire network...
Field programmable gate arrays (FPGAs) potentially offer enhanced reliability, recovery from failures through partial and dynamic reconfigurations, and eliminate the need for redundant hardware typically used in fault-tolerant systems. Our earlier work on scalable self-configurable architectures for reusable space systems (SCARS) describes a partial reconfiguration based self-healing architecture...
We investigate various TCAM architectures recently proposed for TCAM power and memory reduction and show that far better power and memory performance is possible when we use an optimal prefix set for the given routing table than when the original prefix set or the reduced prefix set as proposed in other work is used. For EaseCam, our experiments show a power and TCAM memory reduction of 96% to 98%...
Cryptographic devices are recently implemented with different countermeasures against side channel attacks and fault analysis. Moreover, some usual testing techniques, such as scan chains, are not allowed or restricted for security requirements. In this paper, we analyze the impact that error detecting schemes have on the testability of an implementation of the advanced encryption standard, in particular...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
In this paper we propose a set of different configurations of failure recovery schemes, developed for network-on-chip (NoC) based systems. These configurations exploit the fact that communication in NoCs tends to be partitioned and eventually localized. The failure recovery approach is based on checkpoint and rollback and is aimed towards fast recovery from system or application level failures. The...
The branch and bound (B&B) algorithm is one of the most used methods to solve in an exact way combinatorial optimization problems. In a previous article, we proposed a new approach of the parallel B&B algorithm for distributed systems using the farmer-worker paradigm. However, the new farmer-worker approach has a disadvantage: some nodes of the B&B tree can be explored by several B&B...
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