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Interconnection networks with adaptive routing are susceptible to deadlock, which could lead to performance degradation or system failure. Detecting deadlocks at run-time is challenging because of their highly distributed characteristics. In this paper, we present a deadlock detection method that utilizes run-time Transitive Closure (TC) computation to discover the existence of deadlock-equivalence...
Irregular routing algorithms, as modified if fault tolerant algorithms, can be utilized by irregular networks. These algorithms conventionally use several virtual channels (VCs) to pass faults and oversized nodes. In this paper, a new wormhole-switched routing algorithm for irregular 2-D mesh interconnection Network-on-Chip is proposed, where no VC is used for routing. We also improve message passing...
Reusing on-chip functional interconnects as test access mechanism (TAM) appeared usual these days. One of the most important functional interconnects for highly crowded future system-on-chips (SoCs) is network-on-chip (NoC). Several NoC architectures including router and network interface (NI) have been proposed. They allow narrowcast and multicast of packets, in-order packet delivery, guaranteed...
State of the art VLSI systems are characterised by their small, deca-nano feature size. In order to accommodate the complexity and scalability, a new design paradigm, system on chip (SoC) has been introduced. Performance and power of giga-scale SoC is ever more communication-dominated. However typical SoC communication infrastructure is based in standard buses and protocols which are difficult to...
The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
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