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Over the years, The semiconductor industry has made tremendously impressive improvement in terms of density of very large-scale integrated (VLSI) circuits. Increasing demand for System on Chip(SoC) design can be viewed as a consequence of this trend. In SoC testing, Scan-path test is being used widely to reduce test generation complexity for circuit containing storage devices and feedback paths with...
An approach to test application called transparent scan provides an opportunity to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. The conventional methodology suffers from problems such as high power consumption, less quality results both in terms of pattern count and fault coverage...
In Today's competitive and rapidly changing electronics market, the speed and effectiveness of product testing have a significant impact on time-to-market. You need to make Design-For-Testability (DFT) an essential part of your design process, along with the need for a reliable method of knowing the test coverage and how to improve it. This paper describes the modified Boundary-Scan Register (BSR)...
In a scan-based test architecture, the scan power and and test data volume can be reduced by utilizing a double tree scan (DTS) architecture. This paper presents a novel hardware implementation of the DTS architecture and compares the hardware overhead with the conventional scan architecture. The implementation proposed utilizes a clock structure which greatly decreases the number of clocked flip-flops...
Conventional random access scan (RAS) for testing has lower test application time, low power dissipation, and low test data volume compared to standard serial scan chain based design. In this paper, we present two cluster based techniques, namely, serial input random access scan and variable word length random access scan to reduce test application time even further by exploiting the parallelism among...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
Cryptographic devices are recently implemented with different countermeasures against side channel attacks and fault analysis. Moreover, some usual testing techniques, such as scan chains, are not allowed or restricted for security requirements. In this paper, we analyze the impact that error detecting schemes have on the testability of an implementation of the advanced encryption standard, in particular...
Field programmable gate arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non volatile FPGAs, like Flash-based ones, reduces permanent radiation effects but transient faults are still a concern. In this paper we propose a new methodology for effectively measuring the width of radiation-induced transient faults thus allowing...
In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
The paper addresses the problem of creating a comprehensive fault injection environment, which integrates and improves various simulation and supplementary functions. This is illustrated with experimental results.
The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse. Soft error rate (SER) measurement, expressed as number of failures encountered per billion hours of device operation, is time consuming and involves significant test cost. The cost stems from having to connect a device-under-test to a tester for...
In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order...
Analysis of the tradeoff between hardware overhead, runtime and test data volume is presented when implementing systematic scan reconfiguration using centralised and distributed architectures of the segmented addressable scan, which is an Illinois-scan-based architecture. The results show that the centralised scheme offers better data volume compression, similar automatic test pattern generation (ATPG)...
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