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Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. This paper presents a method for symmetrical FPGA placement based on ant colony optimization (ACO). Also, we take the routing congestion into consideration by introducing a congestion factor in our algorithm. Experimental results show that compared with the state-of-the-art FPGA...
In this paper, we propose a fast routability-driven routing algorithm for hierarchical FPGAs (HFPGAs), using several strategies to steer the automated process of rip up and reroute in order to speed up the process and reach the same effectiveness of Pathfinder's negotiation mechanism. Net is expelled from congestion zone to resourceful zone. The algorithm is divided into two procedures. First, it...
There are generally two options available to integrated circuit (IC) designers to physically implement their designs: synthesis/place and route design and custom circuit design. Each design approach has its advantages and draw backs. This paper will cover a hybrid design flow using concepts from both areas to give us a quick design turn around time while allowing control on custom placement and routing.
Placement profoundly impacts physical design owing to its role in determining the lower bound of a circuit wirelength, as well as the circuit routability. To close the gap between placement and routing, this study integrates global routing and placement to improve the wirelength estimation accuracy of placement. Two methods, called wirelength-reduced cell shifting and cell rearrangement by bipartite...
Escape routing is a critical problem in PCB design. In IC-CAD'07, a layer assignment algorithm was proposed for escape routing of buses. The algorithm is optimal for single layer design in the sense that it determines if a set of buses can all be escaped on one layer. If they cannot, the algorithm is able to select a maximum subset of the buses that can be escaped on one layer. This, in turn, leads...
In this paper, we present an efficient method to solve the obstacle-avoiding rectilinear Steiner tree problem optimally. Our work is developed based on the GeoSteiner approach, modified and extended to allow rectilinear blockages in the routing region. We extended the proofs on the possible topologies of full Steiner tree (FST) to allow blockages, where FST is the basic concept used in GeoSteiner...
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