The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Current networks are changing very fast. Network administrators need more flexible and powerful tools to be able to support new protocols or services very fast. The P4 language provides new level of abstraction for flexible packet processing. Therefore, we have designed new architecture for memory efficient mapping of P4 match/action tables to FPGA. The architecture is based on DCFL algorithm and...
Hash functions represent a fundamental building block of many network security protocols. The SHA-3 hashing algorithm is the most recently developed hash function, and the most secure. Implementation of the SHA-3 hashing algorithm in Hardware Description Language (HDL) is time demanding and tedious to debug. On the other hand, High-Level Synthesis (HLS) tools offer potential solutions to the hardware...
The paper presents the results of design explorations for the implementation of the Smith-Waterman (S-W) algorithm executing DNA and protein sequences alignment. Both design explorations studies and the corresponding FPGA implementations are obtained by writing a dynamic dataflow program implementing the algorithm and by direct high-level synthesis (HLS) to FPGA HDL. The main feature of the obtained...
In recent years, connected component analysis (CCA) has become one of the vital image/video processing algorithms due to its wide-range applicability in the field of computer vision. Numerous applications such as pattern recognition, object detection and image segmentation involve connected component analysis. In the context of camera-based inspection systems, CCA plays an important role for quality...
The cryptographic KECCAK algorithm has been developed by the circuit architect with the objective to enhance the design performances from frequency, throughput, efficiency, power consumption and area viewpoint of. The cryptographic KECCAK algorithm is implemented in many cryptographic circuits to ensure security. It is become the standard algorithm used to ensure the information integrity in numerous...
In the analysis of next-generation DNA sequencing data, Hidden Markov Models (HMMs) are used to perform variant calling between DNA sequences and a reference genome. The PairHMM model is solved by the Forward Algorithm, for which the performance and power efficiency can be increased tremendously using systolic arrays (SAs) in FPGAs. We model the performance characteristics of such SAs, and propose...
This paper presents a hardware architecture for the QR decomposition (QRD) of a complex-valued matrix based on Modified Gram-Schmidt (MGS) algorithm. A high throughput iterative-pipelined design is implemented, which achieves similar performance of a fully parallel-pipelined design, with a significant reduction in hardware usage. For a fixed-point Field Programmable Gate Array (FPGA) implementation...
Internet of things (IoT) is communication between smart objects and human. It finds enormous applications in the field of healthcare monitoring, information management system, agriculture, predicting the natural disaster etc. In all those applications of IoT, security plays a vital role. In this paper, a study on various encryption light weight techniques used for IoT was analyzed. Also the performance...
This paper uses the Altera SDK for OpenCL (AOCL) High-Level Synthesis (HLS) tool to accelerate the computation of the SHA-1 hash function. Using FPGAs to increase throughput of this algorithm has been a popular topic in research. The work done thus far, focuses on HDL based design methodologies. The goal of this paper is to determine if the HLS implementation can compare in terms of speed to the HDL...
Throughput, area and power optimized designs for the advanced encryption standard algorithm are proposed in this paper. The presented designs are suitable for the encrypt-only AES-128 algorithm. Both designs integrate pipelining and iterative architectures in one design. This is achieved through applying the concept of partial loop unrolling where iterations and multistage pipelining are used to optimize...
In this project, a hardware implementation of the AES-256 encryption and decryption algorithm is proposed. The AES cryptography algorithm can be used to encryption and decryption blocks of 128 bits and is capable of using cipher keys of 256 bits. Feature of the proposed pipeline design is depending on the round keys, which are consumed different round of encryption, are generated in parallel way with...
We propose a novel, near-optimal data detection algorithm and a corresponding FPGA design for large multiple-input multiple-output (MIMO) wireless systems. Our algorithm, referred to as TASER (short for triangular approximate semidefinite relaxation), relaxes the maximum-likelihood (ML) detection problem to a semidefinite program and solves a non-convex approximation using a preconditioned forward-backward...
Lenstra-Lenstra-Lovász (LLL) algorithm is a common technique for lattice reduction (LR) aided multiple-input multiple-output (MIMO) detectors. This paper presents the first VLSI implementation of a recently published Incremental fixed-complexity LLL algorithm (Incremental fcLLL) with fewer iterations than other existing fcLLL algorithms. We propose a modified Incremental fcLLL algorithm with simplified...
In the modern world of digitization, processing of data in real time requires an increase in the operating speed of a system. The processing more often than not utilizes multiplication which is time consuming and introduces considerable amount of delay. As such, there is a need to reduce this delay and achieve faster real time processing of data. This paper proposes a novel architecture for implementation...
Following the decision to choose Rijndael as the successor of Data Encryption Standard (DES), Advanced Encryption Standard (AES) was increasingly used in numerous applications which require confidentiality and the secure exchange of the data. While security is a property increasingly sought for many applications (credit cards, telecommunications …), it becomes necessary to consider physical attacks...
The cryptographic hash algorithm has been developed by designers with the goal to enhance its performances in terms of frequency, throughput, power consumption and area. The cryptographic hash algorithm is implemented in many embedded systems to ensure security. It is become the default choice to ensure the information integrity in numerous applications. In this paper, we propose a pipelined architecture...
With the rapid increase of the network bandwidth, to process high throughput regular expressions with hardware has become inevitable. This paper presents a novel NFA-based algorithm. In this paper, two theorems were proved and were used to prove the correctness of the algorithm. Our approach was based on three basic modules to construct NFA that can be easily reused in a FPGA or ASIC. The quantitative...
The increasing data rates expected to be of the order of Gb/s for future wireless systems directly impact the throughput requirements of the modulation and coding systems of the physical layer. In an effort to design a suitable channel coding solution for 5G wireless systems, in this brief we present two approaches to improve the throughput of a Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder...
Symmetric algorithm is a popular encryption algorithms. The proposed algorithm is a class of symmetric algorithm providing an advance security because unlike other symmetric algorithms, the key is not available for users, it is covered and fixed inside the lookup table (LUT) as a part of the FPGA, the design has a fixed operation of encryption created on FPGA device using VHDL language. The paper...
The proposed cryptographic system represents a compact data encryption algorithm (DEA). The implementation provides a short path of encryption and consists of single round. It used only 303 slice and achieved throughput of 278.282 Mbps. The results are shown in the form of chip area performance and performance/slice. The results are compared graphically with similar encryption implementations and...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.