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Bulk FinFETs have emerged as the solution to short-channel effects at the 22-nm technology node and beyond. The capability of 3-D stacking of dies from various technologies will eventually enable stacking FinFET dies within 3-D integrated circuits. Within 3-D circuits, through silicon vias (TSVs) are a known source of substrate noise in planar bulk technologies. While FinFETs are expected to demonstrate...
Substrate noise coupling induced by Through Silicon Vias in SOI substrates is modeled and analyzed in frequency- and time-domain. In addition to a buried oxide layer, a highly doped N+ epi layer used for deep trench devices is taken into account in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A...
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