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In this paper, the implementation of a DSP based video decoder compliant with the H.264/SVC standard (14496-10 Annex G) is presented. A PC-based decoder implementation has been ported to a commercial DSP. Performance optimizations have been carried out improving the initial version performance about 32% and reaching real time for CIF sequences. Moreover, conformance tests have been done using different...
This paper introduces a new method of video-compress based on MPEG-4. The coding algorithm adopts 3-D wavelet transformation and Shape Coding. In hardware implement, DSP chips and FPGA chips is adopted, FPGA completes the task of multiply clock periods operate, while DSP chips accomplishes the function of both the single clock period operate and the control of FPGA relocated calculation. Experimental...
H.264 is the newest high performance video encoding standard that is attributed to applying several new efficient compress methods such as loop filter. The computational time consumed of H.264 increased by 2 or more times compared with previous standard and it hard to implement in many read time or resource-limited application. To speedup the critical time-consuming module, a fast loop filter algorithm...
With the development of the multimedia and network technology, video applications such as VOD, video-phone etc. are used more and more widely in our life. Consider by the high performance and easy implementation, we select TMS320 c6416 DSP platform and implement the MPEG-4 decoder. Based on the architecture and instruction characteristic of DSP, structure-level, program-level, code-level optimization...
Underwater video systems have assumed an increasingly important role in exploration and survey of the unknown deep ocean environments. This paper presents a real-time underwater video compression system that can be mounted on autonomous underwater vehicles (AUVs) for underwater survey applications. The hardware system is based on the digital media processor TMS320DM642 (DM642) of Texas Instruments,...
This paper discusses the optimization of the H.264/AVC video encoder in the context of a modified software implementation on a Texas Instruments TMS320DM642 digital signal processor. Several algorithmic optimizations are proposed to improve time critical parts of the codec like the quantization step and the pixel interpolation. The algorithms proposed in this paper invoke the enhanced direct memory...
This paper describes in detail the various low level optimization techniques for implementing the H.264/AVC video encoding on the TI TMS320DM642 DSP platform. Optimization speedup performance of 5.25 times faster is achieved. A complete AVC encoding and RTSP streaming server system is also developed on the same platform, which is capable of serving live 4CIF video streaming at 25 fps with approximately...
Energy consumption has become an increasingly design issue in multimedia mobile system. This paper presents a realization for suspend/resume on a dual-core SoC to conserve energy consumption while system is idle.A generic backup/restore mechanism is proposed for any DSP applications. Furthermore, optimization for latency targets on characteristic of H.264/AVC decoder is refined and only needs to backup...
Compared with MPEG-4 and other previous standards, H.264 standard has achieved great break through in coding performance. To meet the requirement of embedded video encoder in various scenarios, an H.264 real-time encoder based on TI TMS320C 6455 is presented in this paper. According to the characteristics of the structure, resources and instruction of the selected DSP, a lot of work have been done...
With the rapid development of microprocessor, embedded multimedia products are gradually becoming the mainstream in the market. However, the high coding efficiency enabled by the H.264 video compression standard comes with substantially greater algorithmic complexity as compared to that of existing standards. And this additional complexity results in many difficulties in the implementation and optimization...
Internet protocol set-top boxes (IP STBs) based on single-processor architectures have been recently introduced in the market. In this paper, the implementation of an MPEG-4 simple profile (SP) / advanced simple profile (ASP) video decoder for a multi-format IP STB based on a TMS320DM641 DSP is presented. An initial raw-C decoder for PC platform was fully tested and ported to the DSP. Using this code...
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