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Advanced memory technologies such as DDR4 and LPDDR4 are able to receive and transmit huge amount of data in faster and more efficient ways than ever before. At the same time, reducing power noise and designing dense traces become a challenging part of the design processes. In particular, high signal density on a package naturally restricts the resources for robust power delivery when keeping the...
A substrate coupling analysis and simulation flow for high frequency CMOS system on chip design is presented. It's a straightforward method that can be directly adopted by designers as it only requires commercial design tools. Full chip level simulation including substrate, interconnect parasitics and package is provided in any stage of the design process. A 5 GHz CMOS LNA in the presence of an 88...
A simulation methodology to predict and mitigate interferences between different subsystems in complex mixed-signal system-on-chip ICs at the early stages of a design project is presented. Different aspects of the analysis flow and abstraction levels of the models are discussed. The impact of the floorplan and design choices on circuit performance and the relative contribution of different coupling...
This paper focuses on investigating and modelling the impact of dummy fills on the performance of CMOS spiral inductors. A modified π-Model is proposed to account the dummy effect. A spiral inductor is fabricated on 9-metal 65nm CMOS technology. Dummy effect is evaluated through comparisons on parameter values in equivalent circuit model. Experiment shows the modified π-Model provides proper characterization...
By using inductive coupling, near-field wireless transceivers can be implemented by digital CMOS circuits and on-chip inductors in standard CMOS process without additional process and no restriction of position. Compared with signal-layer inductor, on-chip multilayer inductors have more complicated and irregular structures and lack of process and design support. However, they are still attractive...
In this paper, we present the results of a comparative study performed on six commonly used on-chip differential trace designs in newly emerging 2.5D silicon interposer with high-speed signalling. A generic equivalent circuit model is proposed based on physical geometry. The circuit model is compatible for all the trace structures studied. Impacts of circuit elements in the model are explained theoretically...
A fully integrated framework of full-chip power and substrate noise analysis is discussed, featuring description of transistor-level custom circuits as dynamic noise sources, a high capacity solver for chip-level substrate coupling, and noise back annotation flow to transistors of sensitive circuits. Recursive evaluation of power current and operation timing under the presence of dynamic IR drop greatly...
Real-world realization of RF SoC has been hindered by the lack of high-performance, compact and tunable RF passive devices that are truly CMOS-compatible. This paper presents advances in low-temperature metal MEMS techniques developed to design and fabricate various high-performance RF passives for post-CMOS integration with RF SoC. Constructed with electroplated metal, the RF MEMS passives are suspended...
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