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With the increase in wireless communication technology, encryption of information sent has become a major concern. This involves both the software level and hardware level encryption. GSM was the first cellular system that paid attention to secure mobile communication. Before the advent of GSM the cellular system had no particular security. The GSM voice calls are encrypted using a family of algorithms...
Identifying and removing the undesired stable operating point (also called “Trojan state” in analog circuit) is one of the most important problems in circuit design. In this paper, an innovative divide and contraction verification method against Trojan states is proposed. Unlike the traditional methods to find all operating points, it only targets searching the voltage interval containing undesired...
We present hardware-in-the-loop simulations of a MEMS acceleration sensor system with view to reduce the development time and complexity especially regarding design and test of dedicated control algorithms. To this end, the physically-based high-level Simulink model of the mechanical sensor is connected to a FPGA hardware board, on which the corresponding control algorithms (in our case PID and fuzzy...
Constrained random simulation methodology still plays an important role in hardware verification due to the limited scalability of formal verification, especially for the large and complex design in industry. There are two aspects to measure the stimulus generator which are the quality of the stimulus generated and the efficiency of the generator. In this paper, we propose a self-tuning method to...
This paper presents a new method of automatic test generation for sequential circuits based on particle swarm optimization and ant algorithms. The hybrid algorithm utilizes characteristics of ant algorithm such as positive feedback and keeps basic characteristic of particle swarm optimization to guide the search further. Experiments based on the hybrid algorithm model are implemented. It can achieve...
Outage time after extensive blackouts depends very much on the power system restoration process. Power system restoration is a very challenging task to the operator since the situation is so far from normal conditions. This paper proposes a simulation-based tool that determines a feasible sequence of operator actions that restores power system operation. The effect of each candidate switching operation...
We propose a built-in scheme for generating all patterns of a given deterministic test set T. The scheme is based on grouping the columns of T, so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM)...
Cryptographic devices are recently implemented with different countermeasures against side channel attacks and fault analysis. Moreover, some usual testing techniques, such as scan chains, are not allowed or restricted for security requirements. In this paper, we analyze the impact that error detecting schemes have on the testability of an implementation of the advanced encryption standard, in particular...
The multifractional process is introduced as a natural extension of traditional monofractional process. The selling point of multifractional process is that its Hölder regularity is allowed to vary from point to point, such that makes it a promising model for those stochastic processes whose regularity evolves in time. A new wavelet-based algorithm to synthesize a realization of multifractional process...
It is shown that the problem of deciding and constructing a perfect matching in bipartite graphs G with the polynomial permanents of their n × n adjacency matrices A (perm(A) = nO(1)) are in the deterministic classes NC2 and NC3, respectively. We further design an NC3 algorithm for the problem of constructing all perfect matchings (enumeration problem) in a graph G with a permanent bounded by O(nk)...
We assume a parallel RAM model which allows both concurrent writes and concurrent reads of global memory. Our algorithms are randomized: each processor is allowed an independent random number generator. However our stated resource bounds hold for worst case input with overwhelming likelihood as the input size grows. We give a new parallel algorithm for integer sorting where the integer keys are restricted...
We explicitly construct, for every integer n and ε ≫ 0, a family of functions (psuedo-random bit generators) fn,ε:{0,1}nε → {0,1}n with the following property: for a random seed, the pseudorandom output "looks random" to any polynomial size, constant depth, unbounded fan-in circuit. Moreover, the functions fn,ε themselves can be computed by uniform polynomial size, constant depth circuits...
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