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A higher level, for the Nios II soft processor realizes the IFF encryption authentication technology is discussed in this paper. Through configuration Secure Hash Algorithm (SHA-1) on the Nios II soft processor within Altera FPGA, and communication with the secure EEPROM, an Identification Friend or Foe is completed. This method can provide secure IP protection and license management solution for...
Through the research of current digital signal processing, this paper presents a design with FPGA to achieve FFT, gives the overall implementation framework, and focuses on the design and implementation of the FFT algorithm processing unit, thereby increasing the operation speed of the digital signal processor and reducing the computational complexity.
In this paper, a novel ECC hardware module that provides different secure levels for resource constrained device is introduced. We adopt MOF left-to-right recoding scheme to achieve small area. Moreover, the design reduces the area cost of modular inversion by exploring reusability. Another distinct feature associated with this module is that an MOF based SPA-resistant algorithm is proposed to offer...
The Mellin transform (MT) is a form of a signal representation similar to Fourier transform (FT) which has been widely used in signal processing owing to its distinct properties like scale invariance. In this work, a 2D form of MT which is termed as 2D discrete Mellin transform (DMT) is introduced. The paper also proposes an area efficient, power aware and multiplier less VLSI architecture for 2D...
The computation of shortest path for a mobile automaton between two points in the plane is considered in this paper. An architecturally-efficient solution based on Dijkstra's algorithm is presented for this problem. Results of implementation in Xilinx FPGA are encouraging: the solution operates at approximately 46 MHz and the implementation for a graph with 64 nodes and 88 edges fits in one XCV3200E-FG1156...
Most reconfigurable processors are not fully controlled by software; they are reconfigured using hardware description languages. By moving the data paths into the processor, the system architect can discard the external control logic, the finite state machines and micro-sequencers. Examples for such a processor are the members of the Stretch family, Software Configurable Processors which have a reconfigurable...
This paper presents a scalable and low power low-density parity-check (LDPC) decoder design for the next generation wireless handset SoC. The methodology is based on high level synthesis: PICO (program-in chip-out) tool was used to produce efficient RTL directly from a sequential un-timed C algorithm. We propose two parallel LDPC decoder architectures: (1) per-layer decoding architecture with scalable...
Field programmable gate array (FPGA) was a new material programmable logic units in end of the 20th century, FPGA was with some properties such that, large memory of capacities, short delays of time, improvement able & flexibilities etc. On the basis theory of neural fuzzy system of Networks (NFSN), this paper gives a FPGA method of DNMA (Dynamic Numbers Measuring Algorithm) with VCN (Variable...
Testing and diagnosis techniques play a key role in the advance of semiconductor memory technologies. The challenge of failure detection has attracted investigation on efficient testing and diagnosis algorithm for better fault coverage and diagnostic resolution. March algorithms are widely used in SRAM testing to detect and diagnose SRAM fault model since they are relatively simple and yet providing...
By using small-sized, next-generation NVRAM (such as MRAM, FeRAM and PRAM) as a write buffer, we can improve the overall performance of the NAND flash memory-based storage systems. However, traditional address mapping algorithms in Flash Translation Layer (FTL) software were designed without any consideration of the existence of write buffer. In this paper, we propose a novel write buffer-aware flash...
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