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This brief presents a complementary-to-absolute-temperature voltage and a voltage reference based on the threshold voltage ${\rm V}_{\rm th}$ extraction principle. The proposed ${\rm V}_{\rm th}$ extraction circuit eliminates the nonlinear temperature-dependent mobility and mobility ratio terms, and it achieves a wide operating temperature range from $-25\ ^{\circ}\hbox{C}$ to 250 $^{\circ}\hbox{C}$...
In this paper, an experimental investigation of negative bias temperature instability (NBTI) impact on CMOS inverter circuit is presented. The study focuses on the contribution of NBTI induced PMOS Vth shift on the degradation of the circuit DC features. This investigation was conducted in order to understand the origin of performance shifts due to NBTI at the circuit level and to properly predict...
In this paper, a low-voltage (sub-1 Volt) resistor-free voltage reference is presented. The complete design was simulated and laid out in AMI 0.5 µm CMOS process. The design provides a temperature coefficient of 12.8 ppm/°C over a temperature range from 25 to 100 °C and occupies an area of 0.037 mm2. Circuit description and experimental results of the proposed design are also presented.
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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