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This paper presents the implementation of the novel FIR filter with the filter architecture using shift and add multiplier. The designed is compared to the previous novel FIR designs such as Direct form and previous shift add architecture in Direct form and Transposed form. The design is done on the Transposed structure form of FIR as it is desirable in low power applications. The filters are optimized...
The trade-off between speed and power consumption has become a critical concern as process technology make in-roads to 40nm proximity in modern VLSI technology. We can reduce this trade-off by compensating with accuracy i.e. if an application like Digital signal processing (DSP) can accept some errors then a large power can be saved and at the same time speed can be enhanced. In this paper, we propose...
In this paper we propose a new architecture for an efficient MAC (Multiplier Accumulator Unit) unit with low area consumption which includes Vedic Square as an alternate component in the MAC unit. Vedic Square is based on the principle of Duplex property of Urdhva Tiryagbhya. Using the proposed architecture, 50% of logic gates are reduced from the basic level of 2*2 bit and 12.64% from 16*16 bit square...
COordinate Rotation DIgital Computer (CORDIC) algorithm has become widely researched topic in the field of vector rotated Digital Signal Processing (DSP) applications due to its simplicity. In this paper, we have represented the design of pipelined architecture for the computation of Sine and Cosine values based on application specific CORDIC processor. The design of CORDIC in the circular rotation...
The systematic design of full adder-based architectures for computing a 1-D circular convolution using the Residue Number System is introduced. The proposed architectures consist of three stages that exhibit regular and modular structure. Trade-offs between hardware complexity and speed are achieved by applying partitioning techniques to each stage. Through a recently developed multiplierless algorithm,...
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