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In the last years, research on residue number systems (RNS) has targeted larger dynamic ranges in order to further explore the inherent parallelism of these systems. In this paper, a performance analysis is presented for RNS-to-binary architectures based on New Chinese Remainder Theorem I (New CRT-I). Four different approaches are explored, each of them focused on the area or delay reduction of one...
Many Floating Point operations have been acknowledged to be useful for many real time graphic and multimedia application as well as DSP processors. Many Digital Signal Processing algorithms use Floating point arithmetic, which requires millions of calculations per second to be performed. For such stringent requirements, design of fast, precise and efficient circuits is the goal. This brief presents...
In this work efficient modulo 2n+1 fused multiply-add-add units for weighted and diminished-1 operands are proposed. The proposed architectures can be applied in systems in which fused multiply-add-add units accelerate the execution of the targeting algorithms. Long integer arithmetic would also show considerable gains by using multiply-add-add units. Also, implementation results for the proposed...
In digital signal processing (DSP) applications, large energy gains can be obtained by accepting some degradation in the output signal quality. In this paper, we present static and dynamic techniques for circuit-level timing-error acceptance to significantly improve energy efficiency by shaping the quality-energy tradeoff achievable via aggressive VDD scaling. The proposed techniques specifically...
In this work the most efficient modulo 2n+1 multiplication algorithm for diminished-1 operands proposed to date is extended to compute expressions of the form |A×B + D|2n+1. The derived partial products are reduced by a carry save adder tree to two operands, which are finally added by a modulo 2n+1 adder. The proposed architecture can find applicability in systems in which fused multiply-add units...
COordinate Rotation DIgital Computer (CORDIC) algorithm has become widely researched topic in the field of vector rotated Digital Signal Processing (DSP) applications due to its simplicity. In this paper, we have represented the design of pipelined architecture for the computation of Sine and Cosine values based on application specific CORDIC processor. The design of CORDIC in the circular rotation...
In the area of signal processing, digital circuits are advantageous in terms of lower sensitivity to noise and process variations, simplicity of design, programmability and test, while they attain higher speed, more functionality per chip, lower power dissipation or lower cost. Since some of DSP algorithms heavily rely on multiplication, there are constant demands for more efficient multiplication...
This paper presents fast hardware algorithms for channel operations in the Residue Number System (RNS) in terms of addition, subtraction and multiplication. These algorithms compare favorably with other popular algorithms due to the use of special moduli in the form of 2n - 1. They are particularly applicable for the largest channel or redundant channels in RNS.
Coordinate rotation digital computer (CORDIC) based digital signal processing has become an important tool in consumer, communications, biomedical, and industrial products, providing designers with significant impetus for porting algorithm into architecture. Unfolded implementations of CORDIC algorithm can achieve low latency for rotation and various functions such as division, multiplication, logarithmic...
This paper presents a novel architecture for a high speed finite impulse response (FIR) filter. The design of proposed filter is based on a computation sharing multiplier algorithm with reduced addition implementation. The proposed filter is very efficient, as it gives a significant improvement in speed with a reduction in size of adder circuits. The performance of the proposed filter is compared...
Commonality of various algorithms is analyzed based on the research of algorithms commonly used digital signal processing and a reconfigurable cell is proposed. A reconfigurable system with the cells is designed, which is widely used in a variety of digital signal processing. The principle and method of using this system are discussed with the basic algorithms of digital signal processing - multiplication...
In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR...
Commonality of various algorithms is analyzed based on the research of algorithms commonly used digital signal processing and a reconfigurable cell is proposed. A reconfigurable system with the cells is designed, which is widely used in a variety of digital signal processing. The principle and method of using this system are discussed with the basic algorithms of digital signal processing - multiplication...
FFT algorithm is the popular software design for spectrum analyzer, but doesnpsilat work well for parallel hardware system due to complex calculation and huge memory requirement. Observing the key components of a spectrum analyzer are the intensities for respective frequencies, we propose a Goertzel algorithm to directly extract the intensity factors for respective frequency components in the input...
This paper presents a novel high-speed parallel multiplier based on 3-bit-scan without overlapping bits. The proposed multiplier is able to elaborate both signed and unsigned operands and it is suitable for both full-custom and standard-cells based VLSI implementations. When realized using the ST 90 nm CMOS standard-cells library, the 8x8 version of the novel multiplier exhibits a worst-case delay...
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