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Implementing floating-point (FP) Fast Fourier Transforms (FFT) on Field Programmable Gate Arrays (FPGAs) still represents a challenging task. The limited resources on target devices coupled with the inherent complexity of the FFT are among factors limiting widespread utilization. This paper presents the design of a scalable, FP FFT core for synthesis on Xilinx FPGAs. Its architecture uses a radix-2...
In this paper, we present the design and the implementation of an IEEE 754-compliant floating-point adder with three inputs. The design is based on a 4-level pipeline stage in order to distribute the critical paths and to maximize the performance. We examine the data dependencies to minimize the number of the pipeline stages. The design is customizable to support various floating-point formats, including...
This paper presents an architecture for high-speed bit-parallel multiply-accumulate (MAC) arithmetic operation. This architecture employs the modified-Booth recoding algorithm for multiplication, and a kernel using mixed (sign, value)-encoded signed-binary (SB) and two's complement (TC) computation for carry-free generation of the SB partial-product sums. The final SB partial-product sum undergoes...
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