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An insulated gate bipolar transistor (IGBT) physical model with field stop cell structure is presented in this paper. The extraction method for all parameters is also given here. The parameters are extracted for Fuji Electric 1.7kV/300A IGBT (2MBI300VN-170-50). The accuracy of the model is verified by experiments.
The emergence of silicon carbide MOSFETs and Schottky Barrier Diodes (SBD) at higher voltage and current ratings is opening up new possibilities in the design of energy dense power converters. One of the main advantages of these wide bandgap unipolar devices is the use of fast switching to enable the size reduction of passive components. However, packaging constraints like parasitic inductances limit...
This paper describes an analytical study of synchronous logic gate design based on hybrid structure with MOS and resistive switching non-volatile memories (RS-NVMs). This type of structure allows ultra-low power consumption during power down, while often-used data are saved in RS-NVM cells. The parallel data sensing achieves low-power and fast computation time. The logic gate construction theory,...
The insulated gate bipolar transistor (IGBT) physical models were studied in details, especially Hefner model. A HVIGBT transient physical model is presented in terms of the analysis. The parameters of the model are provided for a typical IGBT of FZ600R65KF1. The test experiment was done and the accuracy of the model was verified. Based on the IGBT model, the difference between HVIGBT and LVIGBT was...
Nanometer CMOS VLSI circuits are highly sensitive to soft errors due to environmental causes such as cosmic radiation, and charged particles. These phenomena, also known as single-event upsets (SEU), induce current pulses at random times and random locations in a digital circuit. In this article, we present a new soft error rate (SER) estimation method for combinational circuits. This method is more...
Along with decrement in size of nanoelectronic devices, they are more prone to the effects of transient faults. Therefore, investigating the effects of such faults is of great importance. Due to high count of transistors in nanoelectronic devices, performing simulation by HSPICE is a time consuming process. Hence, several mathematical models have been proposed. However, our proposed model is simple...
We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric,...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
This paper presents an analytical modeling of ballistic and quasi-ballistic transport, implemented in Verilog-A environment and used for circuit simulation. Our model is based on the Lundstrompsilas approach and uses an expression of the backscattering coefficient given by the flux method. The model takes also into account short channel effects and tales into account the effects of different scattering...
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