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A new bit-line sense amplifier for improving performance in the presence of data-pattern-dependent sensing noise is analyzed. The proposed scheme utilizes the power drop phenomenon in the sense amplifier driving line, resulting in an 81.5% reduction in the amplitude of data-pattern-dependent sensing noise. It is very important to accurately model power drop in compensating data-pattern-dependent sensing...
A low power SRAM macro is customized in 90nm TSMC model technology. The design minimizes the area of the bitcells to achieve a total area of 0.370 mm2. A dynamic supply voltage management scheme is used to reduce the leakage power in the standby mode. The 64 kbits sub-array operates at 1.54 GHz for 1.0V supply voltage. Monte carlo simulation results show that the macro has a 6% failure probability...
This paper presents a method to salvage malfunctioned bits in a FinFET SRAM array caused by random threshold voltage (Vt) variation. The Vt of pass gates (PGs) is gradually lowered during the read process from the initial high value until the stored data is detected by the sense amplifier. As a result, the best Vt is automatically chosen for each cell and malfunctioned bits of both those too fast...
While modern signal detection theory fully accounts for spatially distributed sensors, exploiting these techniques for real-time sensing using large, underwater acoustic arrays requires advances in the spatio-temporal signal processing algorithms. In particular, the computational complexity of many spatio-temporal processing techniques is so large that conventional computer processors lack sufficient...
This paper describes an asymmetric single-ended 6T SRAM bitcell that improves both Read Static Noise Margin (RSNM) and Write Noise Margin (WNM) for the same bitcell area as a conventional symmetric 6T. This improvement is achieved using a single VDD, without employing assist techniques that require multiple voltages. The improvement in noise margins significantly improves the low-voltage robustness...
A nine transistor (9T) cell at a 32nm feature size in CMOS is proposed to accomplish improvements in stability as well as power dissipation compared with previous designs for low-power memory operation. Initially, this paper shows that the proposed 9T SRAM cell can be used for robust, high-density design. Then, an optimum sizing is found for this 9T cell by considering stability, energy consumption,...
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