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On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its topology design, since the topology largely determines its overall performance. For this purpose, they mostly require a switch library which includes all possible switch configurations (e.g. the number of in/output ports and data width)...
Due to the advanced lithography technologies in current semiconductor process, X-architecture has been widely used in VLSI physical design. The architecture contributes more improvements in clock delay, wire length, and power consumption than those of Manhattan architecture. This work proposed an X-architecture zero skew clock tree construction with buffer insertion and sizing. A pattern matching...
The paper presents a new approach for the physical design of integrated circuits where all logic cells are designed on the fly, without the limitations that exists when using a cell library (number of functions, number of transistors, transistor sizing, area and power consumption). A cell generator allows the automatic design of cells having any transistor network (using simple gates or static CMOS...
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