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This paper presents a novel statistical model to estimate the reliability and number of errors of hardware tasks running on partially reconfigurable FPGAs in harsh environments. The proposed model has been validated by means of fault injection. The obtained results endorsed by the 95% confidence interval reveal the high accuracy of the proposed reliability model.
Iterative Stencil Loops (ISLs) are a specific class of algorithms of great importance for their substantial presence in a lot of industrial and scientific computing applications, such as in numerical methods for solving partial differential equation - e.g. reverse time migration and heat distribution simulation - or in cellular automata - used for instance for random number generation and error correction...
Genomics computing is indispensable in basic medical research as well as in practical applications such as disease prevention, pharmaceutical development, and criminal forensics. DNA sequencing, assembly and analysis are key components of genomics computing. Coupled with the increased use of computation for both synthesis and analysis of data in genomics is the astounding increase in the rate at which...
This document is a summary and overview of several approaches to implement the local sequence alignment algorithms known as SWAMP and SWAMP+ on commercially available hardware. Using a Smith-Waterman style of alignment, these parallel algorithms have several innovative extensions that take advantage of the ASC associative computing model while maintaining speed, accuracy, and producing a richer set...
Fault tree analysis of complex systems with repairable components can easily be quite complicated and usually requires significant computer time and power despite significant simplifications. Invariably, software-based solutions, particularly those involving Monte Carlo simulation methods, have been used in practice to compute the top event probability. However, these methods require significant computer...
As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel SoC co-design methodology based on Model Driven Engineering using the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology is...
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