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Associative memories are structures that can retrieve previously stored information given a partial input pattern instead of an explicit address as in indexed memories. A few hardware approaches have recently been introduced for a new family of associative memories based on Sparse-Clustered Networks (SCN) that show attractive features. These architectures are suitable for implementations with low...
ACS (Add-Compare-Select) units are the most important block in FEC (Forward Error Correction) decoders such as Viterbi decoder and Turbo decoder. Due to the increase of performance requirement in next generation mobile communication systems such as LTE-Advanced, high speed operation of ACS units also becomes more important to achieve high throughput requirement. In this paper, we present three types...
Recent work on random access scan (RAS) has shown its advantages in reducing test application time, test data volume and test power over those of the conventional serial scan (SS). This paper is first to examine the soft error tolerance of RAS. The RAS structure not only improves error tolerance ability during test, it also provides capability to efficiently enhance the circuits error tolerance during...
Our paper presents the prototyping of a BCH (Bose, Chaudhuri, and Hocquenghem) encoder and decoder using a Field Programmable Gate Array (FPGA) reconfigurable chip. These types of codes are used in communications networks to detect and correct errors. Typically, the algorithms that implement these codes are sequentially type. Our solution is a combination of a parallel and a sequential implementation...
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