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As technology is scaled down, supply voltage and gate capacitances are reduced which degrades the reliability of the circuits. For near sub-threshold region design, this causes even more serious reliability issues because the supply voltage is reduced to near the threshold voltage of the devices. Soft error is one such phenomenon which changes internal node voltage due to external noise. Hence it...
As CMOS technology is scaled down, the supply voltage and gate capacitance are reduced, which results in the reduction of charge storing capacity at each node and increase of the susceptibility to external noise in radiation environments. In this paper, a novel hardened latch design is proposed and compared with the previous hardened latch designs using 32nm technology node. Extensive simulation results...
High variability in nano-scaled technologies can easily disturb the stability of a carefully designed standard 6T-SRAM cell, causing access failures during a read/write operation. We propose a 7T-SRAM cell to increase the read/write stability under large variations. The proposed design uses a low overhead read/write assist circuitry to increase the noise immunity. Use of an additional transistor and...
In order to explore the feasibility of the large scale subthreshold logic circuits and to clarify the lower limit of supply voltage (VDD) for logic circuits, the dependence of minimum operating voltage (VDDmin) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90-nm CMOS ring oscillators (RO's). The measured average VDDmin of inverter RO's increased...
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