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As technology is scaled down, supply voltage and gate capacitances are reduced which degrades the reliability of the circuits. For near sub-threshold region design, this causes even more serious reliability issues because the supply voltage is reduced to near the threshold voltage of the devices. Soft error is one such phenomenon which changes internal node voltage due to external noise. Hence it...
This paper presents a design of a transmitter pulse generator UWB (Ultra-Wideband) in standard 180nm MOSIS/CMOS technology. We proposed a 5th derivative Gaussian Pulse Generator using a compact Phase Detector (PD) that was designed with dynamic n-blocks and n-latches, and using a delay circuit of a modified pseudo-nMOS inverter architecture. The whole circuit has been simulated using LTSpice and the...
A piecewise linear delay model is accurate to within plusmn10% of SPICE over a wide range of the input transition time. Model accuracy has improved by taking into account the effect of the input slope and short circuit current. Comparisons with SPICE simulation has been observed in several test circuits.
Finite element device level simulations were used in conjunction with SPICE modeling to design and optimize a complementary MOS inverter circuit with an organic p-type and an inorganic n-type transistor combination. The device characteristics of the p-type and the n-type transistors were generated through 2D finite element device level simulations. The drain current (ID) vs. drain-source voltage (V...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
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