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CF card has been widely used in embedded systems development and consumer electronics, due to its high-capacity, nonvolatile data storage,small dimension, easily to be upgraded, shock resistance and other features. In this paper, the interface design between FPGA and the CF was presented, the read and write operations on the CF card were implemented by using FPGA as controller, and high-volume data...
The objective of this work is to design and implement an Image and Video Processing Platform (IVPP) on FGPAs using PICO based HLS. This hardware/software codesign platform has been implemented on a Xilinx Virtex-5 FPGA. The video interface blocks are done in RTL and the initialization phase is done using a MicroBlaze processor allowing the support of multiple video resolutions. This paper discusses...
We propose in this paper, a timing analysis of dynamic partial reconfiguration (PR) applied to a NoC (network on chip) structure inside a FPGA. In the context of a SDR (software defined radio) example, PR is used to dynamically reconfigure a baseband processing block of a 4G telecommunication chain running in real-time (data rates up to 100 Mbps). The results presented show the validity of our methodology...
In this paper, we propose a hardware/software (HW/SW) co-design approach for near real time implementation of high-resolution reconstruction of remote sensing (RS) imagery using systolic arrays as coprocessors. The proposed design is based on a field programmable gate array (FPGA) and implements the image enhancement/reconstruction tasks in an efficient concurrent processing architecture with systolic...
System on Chip (SOC) could be considered as a very useful alternative in the design of real-time systems, especially due to the possibility of integrating several processors in just one FPGA. This strategy enables the use of soft processors to design the systempsilas components, which have traditionally been developed by hardware. In this paper we study a HW/SW codesign of a timer pool for its use...
The PSL-to-Verilog (P2V) compiler can translate a set of assertions about a block-structured software program into a hardware design to be executed concurrently with the program. The assertions validate the correctness of the software program without altering the program's temporal behavior in any way, a result never previously achieved by any online model-checking system. Additionally, the techniques...
In this paper, we present a tool devised for the automatic design and optimization of bioinspired visual processing models using reconfigurable hardware. We have focused on the simulation and optimization characteristics of our system. We also present a retina-like processing system based on a PCI-based FPGA board as an example. The whole system is intended for the design and analysis of real-time...
Recent research has expanded to encompass a view of the reconfigurable logic where a resource is shared among multiple applications or users. Runtime reconfiguration is a method of computing by dynamically changing hardware configurations from phase to phase of a computation. In real-time multitasking system design, task deadlines play an important role as systems not only need to support sharing...
This paper describes the hardware/software co-design of a multithreaded RTOS kernel on a new Xilinx Virtex II Pro FPGA. Our multithreaded RTOS kernel is an integral part of our hybrid thread programming model being developed for hybrid systems which are comprised of both software resident and hardware resident concurrently executing threads. Additionally, we provide new interrupt semantics by migrating...
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