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Parameterisable configurations allow very fast run-time reconfiguration in FPGAs. The main advantage of this new concept is the automated tool flow that converts a hardware design into a more resource-efficient run-time reconfigurable design without a large design effort. In this paper, we show that the automated tool flow for run-time reconfiguration can be used to easily optimize a full hardware...
The EnDat2.2 interface protocol developed by HEIDENHAIN company lately with its high-speed, bi-directional and pure digital features can meet the requirement of rapid responses, dramatically cut down the overall system's cost and greatly reduce the space requirements of the system's installation. Therefore, it is widely used in Numerical control system like CNC system and photoelectric encoder. China's...
The appearance of the new MPEG-4 standard offers opportunities for real-time implementations of MPEG-4 encoders suitable for a wide range of applications, including video conferencing, digital storage media, television broadcasting, Internet streaming, and communication. With the rapid development of FPGA, SOPC has been paid great attentions in the area of image and video processing in recent years...
The discrete wavelet transform (DWT) and the embedded block coding with optimized truncation (EBCOT) account for most of the workload in JPEG2000 encoding. This paper presents a new hardware & software co-design that improves the JPEG2000 encoder's performance while keeping its flexibility by replacing the DWT and the EBCOT with hardware accelerators. In order to further improve the performance,...
This demonstration presents an integrated environment that translates a CAL-based dataflow specification [1] into a heterogeneous implementation, composed by HDL and C codes. The demonstration focuses on the capability of the co-design environment to automatically build an executable heterogeneous system implementation running on a platform composed of a processor and a FPGA from the annotation of...
Existing JPEG2000 2D-DWT architectures all fail to achieve a higher system throughput because they do not exploit the parallelisms fully. In this paper, a high throughput 2D-DWT encoding system is proposed firstly. It exploits three parallelisms of the 2D-DWT algorithm to achieve 1.7 times system throughput over the fastest existing design. For a one-level N times N 2D-DWT, it takes only N2/4 + N...
A hybrid compute system (HCS) combines standard CPUs and reconfigurable devices, usually FPGAs, in one system. These systems have become more attractive again, due to a closer and hence faster coupling of both computational components. From our work with several designs for the same application, we have found the communication between a CPU and a FPGA-based coprocessor to relate either to pipelining...
Muir hardware synthesis process used in the Abhainn design flow for optimisation and implementation of applications on FPGA-centric platforms and specifically its use for multimedia applications. Demonstrated are transformations available at the algorithmic level for an MPEG-2 encoder to reduce the memory usage and increase the throughput of the system. Also examined is the effect manipulations of...
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