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rSesame is a generic modeling and simulation framework which can explore and evaluate reconfigurable systems at the early design stages. The framework can be used to explore different HW/SW partitionings, task mappings and scheduling strategies at both design time and runtime. The framework strives for a high degree of flexibility, ease of use, fast performance and applicability. In this paper, we...
The appearance of the new MPEG-4 standard offers opportunities for real-time implementations of MPEG-4 encoders suitable for a wide range of applications, including video conferencing, digital storage media, television broadcasting, Internet streaming, and communication. With the rapid development of FPGA, SOPC has been paid great attentions in the area of image and video processing in recent years...
The rapid increase in the distribution of digital multimedia data over networks creates the need for copyright protection. Watermarking is one of the techniques that can be used for this copyright protection. Many authors have proposed pure software or hardware solutions for the implementation of watermarking algorithms. In this paper we propose a hardware/software co-design approach for the implementation...
The new generation of field programmable gate array (FPGA) technologies enables an embedded processor intellectual property (IP) and an application IP to be integrated into a system-on-a-programmable-chip (SOPC) developing environment. Therefore, in this paper, we present an efficient HW/SW codesign architecture for JPEG encoder and its FPGA implementation. It consists of a NIOS II processor that...
Embedded systems have been applied widely, not only to consumer products and industrial machines, but also to new applications such as ubiquitous or sensor networking. The increasing role of software (SW) in embedded system development has caused a great demand for embedded SW engineers, and university education for embedded SW engineering has become important. The embedded software engineers should...
This paper presents a methodology for optimization of HW/SW co-design based on emerging configurable processor and FPGA technologies. This methodology is illustrated by the optimization of a discrete cosine transform (DCT) for image compression based on Tensilica's Xtensa LX core and Xilinx Virtex-II Pro device. The various optimization processes of a 2-D DCT transform, including adding different...
In this paper, we present an efficient HW/SW codesign architecture for H.263 video coder and its FPGA implementation. Each module of the coder is investigated to find which approach between HW and SW is better to achieve real-time processing speed as well as flexibility. The hardware portion include the discrete cosine transform (DCT) and inverse DCT (IDCT). Remaining parts were realized in software...
In this paper, we propose an optimized real-time H.263 video coder. The coder has been implemented in one FPGA device as HW/SW partitioned system. We made time analysis and optimization of the H.263 coder. On the basis of the achieved results, we decided for hardware implementation of the discrete cosine transform (DCT). Remaining parts were realized in software with NIOS II softcore processor. H...
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