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High resolution still image compression and storage plays a very important role in the application field of aero military reconnaissance, topography mapping and satellite remote sensing exploration. An embedded high resolution still image compression and storage system based on POWER PC, FPGA and ADV212 is presented in the paper in order to implement 4008×5366×12bit lossy and lossless compression...
Hardware/software co-design is an interesting topic for most embedded system architects. However, designers find integrating hardware and software communications interface challenging. A framework for integrating the software and hardware communication interface for computing in reconfigurable embedded systems, called IRES, is proposed. The framework supports reconfigurable computing architectures,...
The discrete wavelet transform (DWT) and the embedded block coding with optimized truncation (EBCOT) account for most of the workload in JPEG2000 encoding. This paper presents a new hardware & software co-design that improves the JPEG2000 encoder's performance while keeping its flexibility by replacing the DWT and the EBCOT with hardware accelerators. In order to further improve the performance,...
Accelerators are used to speed up demanding computational applications. However, designers find integrating hardware and software communications interface being a challenge. In this paper, the integration methods for computing in reconfigurable embedded systems are explored. Through integration linker, hardware net-list files, tasks, and initial file will be combined into one execution file, which...
The new generation of field programmable gate array (FPGA) technologies enables an embedded processor intellectual property (IP) and an application IP to be integrated into a system-on-a-programmable-chip (SOPC) developing environment. Therefore, in this paper, we present an efficient HW/SW codesign architecture for JPEG encoder and its FPGA implementation. It consists of a NIOS II processor that...
Conjugate-structure algebraic CELP (CS-ACELP) is a type of voice coder algorithm that compresses speech signal based on model parameters of human voice. Fully Software or Hardware implementation of CS-ACELP is not satisfactory in some applications such as multi-channel implementation. So in this paper a hardware-software Co-design implementation of the voice encoder is described. This design is based...
This paper presents a methodology for optimization of HW/SW co-design based on emerging configurable processor and FPGA technologies. This methodology is illustrated by the optimization of a discrete cosine transform (DCT) for image compression based on Tensilica's Xtensa LX core and Xilinx Virtex-II Pro device. The various optimization processes of a 2-D DCT transform, including adding different...
In this paper, we present an efficient HW/SW codesign architecture for H.263 video coder and its FPGA implementation. Each module of the coder is investigated to find which approach between HW and SW is better to achieve real-time processing speed as well as flexibility. The hardware portion include the discrete cosine transform (DCT) and inverse DCT (IDCT). Remaining parts were realized in software...
Muir hardware synthesis process used in the Abhainn design flow for optimisation and implementation of applications on FPGA-centric platforms and specifically its use for multimedia applications. Demonstrated are transformations available at the algorithmic level for an MPEG-2 encoder to reduce the memory usage and increase the throughput of the system. Also examined is the effect manipulations of...
In this paper, we propose an optimized real-time H.263 video coder. The coder has been implemented in one FPGA device as HW/SW partitioned system. We made time analysis and optimization of the H.263 coder. On the basis of the achieved results, we decided for hardware implementation of the discrete cosine transform (DCT). Remaining parts were realized in software with NIOS II softcore processor. H...
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