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We have simulated the coupling ratios in fully planar NAND arrays. We have shown that floating gate interference is no fundamental limitation for channel lengths down to 15 nm. The main limitation for scaling NAND arrays is the loss of control gate coupling due to fringing fields, leading to a strong increase in the programming voltage of the memory cells, even when using a 5 nm EOT IPD.
Since the very beginning of the flash memory era, the market has been dominated by the floating gate technology. However, as floating gate flash continues along a very steep scaling path, more and more barriers start to appear, limiting further scaling possibilities of the technology. At the same time, other concepts are preparing to take over. This paper concentrates on the prospect of high-k materials...
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