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This paper proposes a shared-variable-based approach for fast and accurate multi-core cache coherence simulation. While the intuitive, conventional approach - synchronizing at either every cycle or memory access - gives accurate simulation results, it has poor performance due to huge simulation overloads. We observe that timing synchronization is only needed before shared variable accesses in order...
This work presents a SystemC-based simulation approach for fast performance analysis of parallel software components, using source code annotated with low-level timing properties. In contrast to other source-level approaches for performance analysis, timing attributes obtained from binary code can be annotated even if compiler optimizations are used without requiring changes in the compiler. To consider...
The number and complexity of attacks on computer systems are increasing. This growth necessitates proper defense mechanisms. Intrusion detection systems play an important role in detecting and disrupting attacks before they can compromise software. Multivariant execution is an intrusion detection mechanism that executes several slightly different versions, called variants, of the same program in lockstep...
OpenMP is a widely used parallel programming model on traditional multi-core processors. Generally, OpenMP is used to develop fine-grained parallelism through a multi-thread model. Stream programming model is a new kind of parallel programming model for stream architectures. OpenMP bears a resemblance to the stream programming model at some level. The transformation between the two models has attracted...
Writing software for distributed systems is a complex task and gets even harder when shared data is replicated among nodes. Transactional memory is a promising technology for dealing with both synchronization and data consistency issues. Rainbow OS, a distributed operating system for PC clusters, employs this concept in a distributed fashion providing a cluster-wide transactional distributed memory...
Time-consuming cycle-accurate MPSoC simulation is often needed for debugging and verification. Its practicability is put at risk by the growing MPSoC complexity. This work presents a conservative synchronous parallel simulation approach along with a SystemC framework to accelerate tightly-coupled MPSoC simulations on multi-core hosts. Key contribution is the implementation strategy, which utilizes...
As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore's law, the computing industry has switched its route to higher performance through parallel processing. The rise of multicore systems in all domains of computing has opened the door to heterogeneous multiprocessor, where processors of different compute characteristics can be combined...
The Gauss-Seidel method is very efficient for solving problems such as tightly-coupled constraints with possible redundancies. However, the underlying algorithm is inherently sequential. Previous works have exploited sparsity in the system matrix to extract parallelism. In this paper, we propose to study several parallelization schemes for fully-coupled systems, unable to be parallelized by existing...
This work focuses on the HW/SW co-simulation of complex systems consisting of several independent CPUpsilas (multi-CPU systems) such as multi-processor system-on-chip (MPSoC) and wireless sensor networks. The verification of such systems requires the efficient evaluation of hardware-software interactions in several processing units. We present a HW/SW co-simulation framework consisting of a timing-accurate...
When running multiple e-Business server applications simultaneously on the same hardware, inappropriate CPU sharing may endanger the performance stability for individual applications. Robustness and manageability are critical for Java server applications on emerging multi-processing hardware platforms. This paper investigates the performance implications of multiprocessing (including SMP and CMP)...
The Sequoia computer is a tightly coupled multiprocessor that avoids most of the fault-tolerance disadvantages of tight coupling by using a fault-tolerant hardware-design approach. An overview is give of how the hardware architecture and operating system (OS) work together to provide a high degree of fault tolerance with good system performance. A description of hardware is followed by a discussion...
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