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A low-power programmable processor named icyflex1 was designed combining features of a digital signal processor (DSP) and a micro-controller unit (MCU). Implemented as a synthesizable VHDL software intellectual property core, the processor implements a broad range of power saving features including its customizable architecture and reconfigurable instruction set. Its performance is compared with other...
This paper presents a design of AES (advanced encryption standard) with parallel architecture. The proposed architecture maintains throughput as it is but consumes lower power than the original architecture by using 1/2 clock-rate and reducing supply voltage. Models were designed using VHDL and verified by both functional and gate-level simulation. They were logically synthesized using 0.25 um, 90...
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