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Various physical layer protocols are employed to encode information bits in short range wireless communication technologies. In this paper, we propose a multimode hardware architecture for a digital baseband encoder which incorporates Manchester, Differential Manchester and FM0 codes. These codes help in achieving good DC balance thereby improving signal reliability. Alternating Manchester with Differential...
This paper describes the architecture and VLSI (very large scale integration) implementation of a direct digital frequency synthesizer (DDFS) based on a hybrid CORDIC (COordinate Rotation DIgital Computer) algorithm. It is shown that the architecture can be implemented as a multiplier-less, small ROM ( 4 times 16 -bit) and pipelined data path. A SoC (system on chip) has been designed with 0.18 mum...
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