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In recent years, as the VLSI process scale had been developed into deep sub-micro dimension, the problem of the routing delay becomes critical. Especially for reconfigurable logic devices (RLDs) like Field Programmable Gate Arrays (FPGAs), the routing resources occupy approximately 90% of area and delay performance. In this paper, we propose a novel 3D routing architecture based on building 3D connections...
We propose a variable grain logic cell (VGLC) architecture. Its key feature is variable granularity which helps to create a balance between two types of devices: coarse-grain type and fine-grain type. Because of this, the VGLC can achieved high-performance on any applications. In this paper, we describe the VGLC prototype chip designed in e-Shuttle 65nm library. In addition, in order to implement...
As process geometries shrink, the nonrecurring engineering (NRE) cost is increasing; the ability to make post-fabrication changes to system-on-chip (SoC) is becoming more and more attractive. This ability can be realized by embedding a PLC (programmable logic core) into a SoC. However, the design of PLC is a complex and daunting process; there are many issues to be addressed such as architecture,...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
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