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Population aging has become a worldwide problem. Fall accidents are considered as one of the major health risks, especially for elderly people. Fall detection devices are the key to distinguish a fall from daily activities, automatically alert when a fall occurred and significantly decrease the time of rescue when the monitored patient falls down. The proposed prototype is composed of a tri-axial...
In this paper, we present two novel real-time heterogeneous platforms with three kinds of devices (CPU, GPU, FPGA), i.e. trigeneous platforms, for efficiently accelerating computation intensive applications in both the high-performance computing and the embedded system domains. In the high-performance computing domain, the entire platform is implemented on a workstation which consists of an Intel...
Specialization and accelerators are being proposed as an effective way to address the slowdown of Dennard scaling. DySER is one such accelerator, which dynamically synthesizes large compound functional units to match program regions, using a co-designed compiler and microarchitecture. We have completed a full prototype implementation of DySER integrated into the OpenSPARC processor (called SPARC-DySER),...
Most of scientists except computer scientists do not want to make efforts for performance tuning with rewriting their MPI applications. In addition, the number of processing elements which can be used by them is increasing year by year. On large-scale parallel systems, the number of accumulated messages on a message buffer tends to increase in some of their applications. Since searching message queue...
This paper presents a hardware accelerated NIOS-II implementation of a Turbo decoder. Firstly, a Matlab prototype consisting of a) an encoder made of a parallel concatenation of two RSC encoders and b) a decoder based on two identical SOVA decoders is constructed. Simulations of the prototype show that the BER decreases for every iteration in the decoder (down to 10-4), except for low SNR cases (below...
According to the specified standard of airborne Photogrammetry, digital airborne cameras must have higher performance than ordinary civil cameras, which must shoot with shorter time interval and will generate huge data stream. In this paper, a digital airborne camera is designed and implemented in a single FPGA chip as a SOPC approach. The functions of image acquisition, storage and display are implemented...
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