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Networks-on-chip (NoCs) have become a de facto communication standard for many core systems-on-chip (SoCs). A NoC has large design space composed of several parameters such as routing algorithm, task mapping, among others. SoC designers deeply rely on automatic evaluation tools in order to deal with the complexity of NoC design. An important class of NoCs evaluation tools are the platforms based on...
SRAM-Based FPGAs are widely employed in space and avionics computing. The unfriendly environment and FPGA radiation sensibility can have dramatic drawbacks on the application reliability. The partial self-reconfiguration ability gives an excellent aid to counteract single event upsets (SEUs) caused by excessive silicon ionization, and the consequent system misbehavior. Related to this feature, fault...
Dramatic increases in embedded data processing performance are becoming possible using platforms such as the NASA SpaceCube. With a flexible architecture and commercial devices, selected computations can be tuned for the highest performance while giving up perfect data reliability. More needs to be known about the nature of silent data corruption in this paradigm. When it occurs, how pervasive is...
In this paper a testbed for evaluating 802.11 wireless devices as part of a wireless mesh network has been presented. Full design details of this instrumentation have been given. Whilst full RF emulation is not supported by this testbed, a large range of topologies and wireless environments can be accurately modelled for wireless experimentation. The operation of the developed testbed has been demonstrated...
This paper presents the design and performance measurement of the hardware JPEG codec on an ARM926EJS emulation base board. JPEG is one of the best compression algorithms for still images. It preserves the quality with high compression ratio. JPEG codec encodes and decodes coloured as well grey image formats. The design exploits the pipeline architecture for high throughput. Overall size of the codec...
We present an efficient emulation-based technique to accelerate architecture exploration of networks-on-chip (NoCs). The large design space of NoC along with its growing complexity that results in low simulation speeds on host machines have motivated the need for hardware accelerators for speeding up the simulation. For example, simulation of applications with real life problem sizes could take weeks...
HW/SW co-emulation technique combing software simulation with hardware acceleration is one of the popular techniques for SOC verification, where interrupt-based communication mechanism is usually utilized. However, communication overhead will be resulted from data exchange between hardware side and software side at every cycle. A stream-mode based HW/SW co-emulation technique is proposed and presented...
In this paper, we study and compare the performance of bus-based and mesh-based with spidernet NoC-based infrastructure in Alterapsilas FPGA. We first analysis the inner latency performance of the NoC infrastructure among routers, and we provide two modes to emulate the specific application on those infrastructures for the purpose of performance comparison. It is shown that NoC-based infrastructure...
The emulation and functional validation are essential to assessment of the correctness and performance of networks-on-chip architecture. A flexible hardware/software networks-on-chip open platform (NoCOP) emulation framework is designed and implemented for exploring the on-chip interconnection networks architecture. An instruction set simulator and universal serial bus communicator control and configure...
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