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This paper characterizes the scaling of maximum frequency in lower-performance and higher-performance field-programmable gate-array (FPGA) chips as a function of circuit size and complexity. The evaluation is based on synthesizing mesh and toroid circuit topologies with parameterized node count and interconnect width. Each node accepts two input bit vectors and generates two output bit vectors, and...
The paper proposes high speed FPGA implementations of adders and multipliers in Fp. The work shows through experimental results that due to optimized addition chain available in such devices, Karatsuba decomposition upto a particular level improves the performance. Further the paper modifies existing interleaved multiplier using Montgomery ladder and the high speed adder circuits. Extensive experiments...
Many scientific applications such as electromagnetics require their operations carried out in double-precision floating-point format. The efficiency of these applications is mainly subject to the floating-point processing performance on the target processors. In this work, we use an eigenvalue solver application as a case study to demonstrate the processing potential of an FPGA device when dealing...
This paper presents a novel architecture optimized for realizing efficient absolute difference circuits in Virtex-5 FPGA devices. The proposed structure efficiently uses the 6-input look-up-tables available within the chosen devices family to maximize speed performance and to minimize the amount of occupied resources. In comparison with the DSP- and the LUT-based absolute difference circuits automatically...
The use of redundant number systems can significantly improve computational performance in numerically intensive applications, however, the implementation of their arithmetic circuits is usually expensive because multiple bits are needed for each symbol (digit). This paper presents efficient adder circuits specifically targeted to the low cost FPGA architectures of the Xilinx Spartan 3 and the Altera...
The performance/area characteristics of a Sigma Delta Modulated Ternary FIR filter and a conventional FIR filter are compared. The implementation of both filters has been carried out in VHDL using a hierarchical adder tree organization in both pipelined and non-pipelined modes and synthesized on a small number of representative commercial FPGA devices. At a similar spectral performance, the ternary...
This paper introduces an embedded speech recognition system, including both hardware and software frameworks, based on an FPGA platform and the HMM algorithm. The paper also proposes an approach to the design and implementation of an IP core for the forward algorithm, as well as simulating the algorithm. The main advantage of this approach is the reduction of processing time in speech recognition...
Fast Fourier Transform (FFT) is the most basic and essential part of Software Defined Radio (SDR). Therefore, designing regular, reconfigurable, modular and low hardware complexity FFT computation block is very important. A single FFT block should be configurable for varying length FFT computation and also for computation of different transforms like DCT, DST etc. In this paper, the authors analyze...
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