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A 12-channal 120-Gb/s optical receiver front-end amplifier array has been designed in a 0.18-μm CMOS process. This front-end amplifier array incorporates transimpedance amplifiers (TIAs) and limiting amplifiers (LAs). A regulated cascode (RGC) input structure, active inductor peaking and feedback technique are exploited to enhance the bandwidth without deterioration of the other performances. And...
Analysis and optimization process of single stage low power low noise amplifier (LNA) in CMOS technology has been presented. Input and output matching networks has been designed using derived analytic equations. Noise figure of LNA has been analyzed using accurate noise model for various noise contributors, including both of transistors in the cascode stage and substrate. Optimization process has...
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises superiority in exploring the flexibility offered by a design over all previous representation methods. In this work, we illustrate how the SPFD of a particular wire reveals information regarding the number of potential transient...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
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