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The design of analog and radio-frequency (RF) circuits in CMOS technology has become increasingly more difficult as device modeling faces new challenges in the deep sub micrometer regime and emerging circuit applications. Double gate MOSFETs show greater promise in this regard with improved short channel effects, high gate control and reduced leakage. But still they may be engineered for better performances...
While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and SRAM cells. FinFET SRAMs are shown to have excellent VDD scalability (SNM=185 mV at 0.6 V), enabling sub-32 nm low-voltage design.
Scaling of CMOS transistors beyond 45 nm requires architectural redesign of the devices. FinFETs are proposed to recover the reduced channel control. This work evaluates the perspective of RF design in planar bulk vs. FinFET SOI for (sub-)45 nm CMOS on a key RF circuit: a low-noise amplifier (LNA). The planar and FinFET devices with channel lengths down to 40 nm are compared in both wideband and narrowband...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
FinFET technology presents a competitive alternative to planar CMOS as it features a better control of the short channel effects. This results in improved digital and analog performances. The radio-frequency (RF) behavior is however affected by a large level of parasitics. In this paper, we explain how technological options and device design affect the FinFET performance. In addition, the challenges...
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