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Channel mobility μeff for InGaAs MISFETs is improved by using the (111)A surface orientation and (NH4)2S treatment. These μeff improvements are associated with negative shifts in Vth and Vfb. We propose that carrier scattering by fluctuated dipoles at the MIS interfaces contributes to μeff for the III-V MISFETs. For the InP MISFETs, the effects of the interface dipoles are not apparent due to their...
We would like to report our approaches to realize epitaxially grown source toward high drain current in III-V MISFET. One approach is an InP/InGaAs composite channel MISFET with regrown InGaAs source/drain. When gate length of 150 nm was fabricated, Id at Vd = 0.8 V was 0.8 A/mm and maximum gm was 0.38 S/mm at Vd = 0.5 V. The other approach is vertical FET. In case of vertical FET with dual gate,...
It is important for shrinking the mesa width of a channel region in a vertical InGaAs channel MISFET for carrying out high-speed operation and for obtaining a steep sub-threshold slope. Therefore, we introduced selective undercut etching after the dry etching of the mesa structure. In the fabricated device with 60-nm-long channel, the channel mesa width became 15 nm. The maximum drain current density...
In this paper, we report the catalyst-free growth of nanowires utilizing selective-area metalorganic vapor-phase epitaxy (SA-MOVPE) and their application to FETs. InAs nanowire FETs with Schottky gate resulted in large gate leakage current. But the leakage current was suppressed by using a MIS gate structure, and good saturation characteristics as FET were obtained.
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