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Quantum well field effect transistors have been proposed as promising device candidates for future high-speed and low-power logic applications due to their high electron mobility. This paper aims to study InAs and InGaAs state-of-the-art QWFETs, investigating both RF and DC performance through our full band Cellular Monte Carlo simulator, which includes the full details of the band structure and the...
Small-bandgap InAs channel materials are potential candidates for high-speed and low-power applications and have been demonstrated in AlSb/InAs/AlSb QWFETs. Taking advantage of their excellent transport properties, we successfully develop an InAs-channel metal-oxide-semiconductor modulation-doped field-effect transistor (MOS-MODFET) using 100-nm PECVD-deposited SiO2 dielectrics for gate dielectrics...
We have experimentally investigated the trade-offs involved in thinning down the channel of III-V FETs with the ultimate goal of enhancing the electrostatic integrity and scalability of these devices. To do so, we have fabricated InAs HEMTs with a channel thickness of tch = 5 nm and we have compared them against, InAs HEMTs with tch = 10 nm. The fabricated thin-channel devices exhibit outstanding...
We have built a physical gate capacitance model for III-V FETs that incorporates quantum capacitance and centroid capacitance in the channel. We verified its validity with simulations (Nextnano) and experimental measurements on High Electron Mobility Transistors (HEMTs) with InAs and InGaAs channels down to 30 nm in gate length. Our model confirms that in the operational range of these devices, the...
The scaling behavior of ultra-scaled InAs HEMTs is investigated using a 2-dimensional real-space effective mass ballistic quantum transport simulator. The simulation methodology is first benchmarked against experimental Id-Vgs data obtained from devices with gate lengths ranging from 30 to 50 nm, where a good quantitative match is obtained. It is then applied to optimize the logic performance of not-yet-fabricated...
We theoretically estimate the performance limits of the effective injection velocity, vs, and fT in the nano-scale InAs HEMTs using the quantum-corrected Monte Carlo (MC) method. The negative tail of the momentum distribution function, f(x, kx) at the potential bottleneck is caused by the electron scatterings. As Lg decreases, the negative tail decreases: which results in the increase of vs. Because...
High-performance 130 nm E-mode InAs p-HEMTs is fabricated using the Ne-based ALET and the buried Pt gate technology. Results from the combination of the improved gate-to-channel aspect ratio achieved by the buried Pt gate technology show that performance of the device is remarkable and the improved carrier transport property is achieved using the ALET technology.
Maximizing In composition in the channel structures of high-electron-mobility transistors on InP is one important aspect of achieving devices capable of operating beyond 300 GHz. In this article, we compare dc and rf performance results from two variations of one such device design, incorporating a composite-channel structure comprised of InAs clad by InP-lattice-matched InGaAs. The only difference...
80-nm high electron mobility transistors (HEMTs) with different indium content in InxGa1-xAs channel from 52%, 70% to 100% have been fabricated. Device performance degradation were observed on the DC measurement and RF characteristics caused by impact ionization at different drain bias, >0.8 V (InAs/In0.7Ga0.3As), >1 V (In0.7Ga0.3As) and >1.5 V (In0.52Ga0.48As), respectively. The impact ionization...
An 80-nm InP HEMT with InAs channel and InGaAs sub-channels has been fabricated. The high current gain cutoff frequency (ft) of 350 GHz and maximum oscillation frequency (fmax) of 360 GHz were obtained at VDS = 0.7 V due to the high electron mobility in the InAs channel. DC and RF characterizations on the device have been performed and the on- sate breakdown voltage of the device was measured to be...
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