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A fully integrated CMOS GPS receiver RF front-end is presented. Systematic circuit optimizations for ultra-low voltage operation including subthreshold biasing, a novel mixer-VCO interface, and charge neutralization enable the supply voltage to be dramatically reduced as a means to save power. The 250 mV supply is the lowest ever reported for any integrated receiver RF front-end to date. Its 352 μW...
The performance of on-chip passives and their application at mm-wave frequencies in two key silicon technologies are presented in this paper. Power and linear combiners designed in advanced 130 nm SiGe-BiCMOS and 65 nm CMOS-SOI are used as demonstrators. Multi-port transformer and shielded-CPW-on-SOI power combiners realize insertion loss as low as 0.5 dB and reflected port to port impedance uniformity...
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