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We present a multi-core virtual platform which follows single-core architecture, SPARC v8, available as an open source development suite. The proposed multi-SPARC system operates at electronic system level to accelerate its simulation speed. TLM channels are devised to connect the processors. To simplify the use of the proposed virtual platform, we define some specific APIs for data transaction and...
Multi-core platforms are becoming the dominant computing architecture for next generation embedded systems. Nevertheless, designing, programming, and analyzing such systems is not easy and a solid methodology is still missing. In this paper, we propose two powerful abstractions to model the computing power of a parallel machine, which provide a general interface for developing and analyzing real-time...
Increasingly more computing power is demanded for contemporary applications such as multimedia, 3D visualization, and telecommunication. This paper presents a design space exploration (DSE) experience for an embedded VLIW processor that allows finding out the best architecture for given application. The proposed method has been implemented and tested using an image processing chain for direct photo...
The increasing complexity of embedded systems imposes system designers to use higher levels of abstraction than RTL in order to model, validate and analyze a system performances. It permits to prevent costly redesign efforts at RTL, which can adversely affect time-to-market. For this purpose transaction level modeling (TLM) approach is used. It allows the designers to rapidly verify and develop their...
As implementation architectures for complex systems evolve towards heterogeneous multiprocessing, let this be on a single chip or on a geographically distributed area, the importance of communication has reached unprecedented peaks. Indeed, due to the complex nature of interaction among its components, any complex system has behaviors that may be highly unpredictable. Dealing with such behaviors requires...
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